reference.com
It should have been famous within the text that a lot of the outline of multi-cache interaction is specific to x86 and similarly “sequentially-consistent” architectures. Most modern architectures aren't sequentially constant, and threaded packages should be extraordinarily cautious about one thread depending on knowledge written by another thread turning into seen within the order through which it was written. Alpha, PPC, Itanium, and (sometimes) SPARC, MemoryWave Guide but not x86, AMD, or MIPS. The consequence of the requirement to take care of sequential consistency is poor performance and/or horrifyingly complicated cache interaction equipment on machines with greater than (about) 4 CPUs, so we are able to expect to see extra non-x86 multi-core chips in use quickly. I think your criticism is misdirected. The textual content does not touch on memory consistency in any respect - it's solely out of its scope. Apart from, you need a cache coherency protocol on any multi processor system. With regards to memory consistency, there are different opinions.

Some time ago there was a very attention-grabbing discussion in RealWorldTech the place Linus Torvalds made an interesting point that it may be argued that specific memory obstacles are dearer than what the CPU has to do with a purpose to create the illusion of sequential memory consistency, because specific MBs are by necessity more general and actually have stronger guarantees. Sorry, not true. It describes how caches of various x86 CPUs interact, but would not say it only describes x86, falsely suggesting that is how each other machine does it too. It leaves the reasonable reader below the impression that programmers needn't know anything about memory consistency. That is not totally true even on x86, but is just false on most non-x86 platforms. If Ulrich is writing for folks programming solely x86, the article ought to say so with out quibbling. If not, it ought to call out locations the place it's describing x86-specific behavior. To the better of my information, the outline within the article applies to all cache coherent methods, together with the ones listed in your previous post.

It has nothing to do with memory consistency, which is an issue mostly inner to the CPU. I'm very possibly fallacious, after all - I am not a hardware system designer - so I'm glad to debate it. Can you describe how the cache/memory behavior in an Alpha (for instance